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| Thought Paper |
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Evaluating and Improving Emulator Performance |
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| Abstract |
With functional verification becoming the largest task in the development of an ASIC or large FPGA, many engineers are looking at simulation acceleration or emulation as a way to speed development. Engineers today can choose from a number of different platforms.
Specifications or performance metrics from the various vendors have been expressed as gate capacities, speed-up ratios over simulation, bandwidth and/or clock frequency of the acceleration hardware. These metrics are not easily compared across vendors, and terminology is not always consistent. On a given emulator, actual performance varies widely according to the specific target design. Even for a given design, mapped to a given emulator platform, execution times for different tests vary widely.
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