| |
| Thought Paper |
| |
FPGA-Based Systems: To Verify or Not To Verify |
| |
| Abstract |
FPGAs are wonderful devices. They allow changes to be made relatively easily compared to ASICs. Their design flows are not that different from ASICs, and in fact, the flow is a bit easier to understand for the novice. In addition, FPGAs, like ASICs, are allowing ever greater logic densities for designers to use for their systems - more with less, so to speak.
However, it has been my experience that FPGA-based systems can lure inexperienced system designers into a trap. The logic goes something like "if it doesn't work, we can fix it in the lab!"
This paper will provide a more rigorous approach to understanding the verification problem as it relates to FPGA-based systems. To illustrate the approach and results, a real system will be used as an example.
|
