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| Thought Paper |
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Methodology and Code Reuse in the
Verification of SOCs |
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| Abstract |
The ever-competitive market pushes semiconductor IC designs to be packaged on larger dies, incorporating more functionality. In order to achieve the 'time-to-market' targets, semiconductor companies incorporate important blocks and cores, developed and verified by other companies, into their chips. This reuse of outsourced intellectual properties (IP) into a larger IC design thus led to the creation of System-on-Chip (SOC) designs. The resulting SOC complexity, cost and increased probability of errors raised the importance of verification. Every stage of the IC design flow requires a certain degree of verification, which, in turn, contributes to the overall chip cost and quality. Obviously the detection of RTL errors in SOCs minimizes the cost of fixing them at the later stages
The verification of SOCs involves heavy simulations of large amounts of data, extending the RTL debug cycle. Synopsys developed a set of workbenches to provide for the verification of ASIC design compliance to the ATM, SDH and SONET standards. By providing standard library modules and ready-to-use testbenches, Synopsys offers an easy-to-use verification framework but does not address the problem of speeding up the SOC simulation cycles. C-based testbenches offer effective solutions to boost the simulation and emulation performance. However, the lack of a flexible verification environment with code reuse across projects keeps the verification costs high.
Sun Microsystems developed an object-oriented approach to the verification of complex ASICs using C++. The described verification system is based on a framework developed with the goal of being extensible and reusable. However, the proposed testbench reusability is limited. Synopsys offers a specialized verification language called Vera. Vera extends the level of abstraction of such languages like C++ and Java to model and verify hardware. A set of tools developed around Vera leverages the development of verification testbenches that may contain a mixture of Vera, HDL and C/C++ code. Nevertheless, the Vera-C interface is not straightforward and implies some limitations to the C code complexity. In addition, mastering Vera requires special training and practice, which affects time to market and therefore product cost.
This paper discusses a verification framework and methodology exploited in verification projects of SOCs.
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